Actis VSBC-6862 Specifiche Pagina 1

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Rev. 1.43 User's Guide 91.3. Photograph Figure 1: Photograph The VMEbus Technology logo is a Trademark of the VMEbus International

Rev. 1.43 User's Guide 997 Registers definition IPGCRA IP General Configuration Register A RW CS4 + $401 IPGCRB IP

VSBC-6862 Rev 1.43 100 IPDCRA IP DMA Configuration Register A RW CS4 + $403 IPDCRB IP DMA Configuration Register B RW CS4 +

Rev. 1.43 User's Guide 101IPIVRA IP Interrupt Vector Register A RO CS4 + $481 IPIVRB IP Interrupt Vector Register B

VSBC-6862 Rev 1.43 102 SRESR Software Reset Register WO CS4 + $1001 VME slave + $9 This register permits to perform Software or Har

Rev. 1.43 User's Guide 103BSCR Board Special Configuration Register RW CS4 + $1021 This register permits to access the pr

VSBC-6862 Rev 1.43 104 VMBA VME Master Bus Access RW CS4 + $1051 This register permits to select the mode for VME bus access and r

Rev. 1.43 User's Guide 105VMBMA VME Master: A32 Base address for window A RW CS4 + $1055 VMBMB VME Master: A32 Base address

VSBC-6862 Rev 1.43 106 VHIL VME interrupt Handler: Interrupt Level RO CS4 + $1061 This register indicates the current VME interrupt

Rev. 1.43 User's Guide 107VHV VME Interrupter Vector RO CS4 + $1073 to CS4 + $107f When accessed, this register acknow

VSBC-6862 Rev 1.43 108 VIVEC VME Interrupter Vector RW CS4 + $106d VME slave + 7 This register contains IRQ level and the vector

VSBC-6862 Rev 1.43 10 1.4. Block diagram The VSBC-6862 architecture is divided in four main sections: The CPU This is the heart of the board,

Rev. 1.43 User's Guide 109VSBA24 VME Slave Base Window A24 RW CS4 + $1069 VME slave + 3 This register sets the VME base addre

VSBC-6862 Rev 1.43 110 VSWA24 VME Slave Window A24 management RW CS4 + $106b VME slave + 5 This register contains the local offsets f

Rev. 1.43 User's Guide 1118 Characteristics Electrical characteristics PARAMETER MIN TYP MAX UNITSPOWER SUPPLY +5 V (VD

VSBC-6862 Rev 1.43 112 Performance issues The VSBC-6862 has been designed for providing efficient performance with peripheral connected around

Rev. 1.43 User's Guide 1139 Physical board definition 9.1. PCB dimensions 1.7mm160mm Figure 22: PCB dimensions Artisan Technology Gr

VSBC-6862 Rev 1.43 114 9.2. Front panel Figure 23: Front panel Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 8

Rev. 1.43 User's Guide 11510 Software available Thanks to ECRIN Automatismes, many software packages are already available for the

VSBC-6862 Rev 1.43 116 The boot time is less then 1 second. Then, when typing the 'Return' key, the 'ECMon>' prompt wi

Rev. 1.43 User's Guide 117i2c Function : Read or write data from/to an I2C device Syntax : i2c <device> <offset> &

VSBC-6862 Rev 1.43 118 mmap Function : Display memory map Syntax : mmap mmb, mmw, mml Function : Modify the contents of memory (byt

Rev. 1.43 User's Guide 111.5. Component location Figure 3: Component location Artisan Technology Group - Quality Instrumentation ...

Rev. 1.43 User's Guide 119pflash Function : Program flash memory Syntax : pflash <source> <count> <destination&

VSBC-6862 Rev 1.43 120 10.2.3. Typical example The following example will describe the procedure to use the second Flash memory bank as user&a

Rev. 1.43 User's Guide 12111 Hardware available One of the main advantage of the VSBC-6862 is his versatility. Through its IP and/o

VSBC-6862 Rev 1.43 122 LAN-15 MIL-STD-1553 Bus controller (BC), Remote terminal (RT), and Bus monitor (MT) with 64K x 16 bit of RAM (to support

Rev. 1.43 User's Guide 12311.2. List of ACTIS's 6U transition modules The IP modules provides many functions, some of these fu

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Rev. 1.43 User's Guide 12512 Technical support Should you encounter any trouble during installation or hardware operation of your

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Rev. 1.43 User's Guide 12713 Ordering information VSBC-6862/200-128-16 VME board with MPC-8260 @ 200 MHz 128 MBytes SDRAM,

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VSBC-6862 Rev 1.43 12 Please note that on the VSBC-6862, some locations are not populated. This was done either to avoid problems of component

Rev. 1.43 User's Guide 12914 OEM Warranty ACTIS Computer, warrants your VSBC-6862 board against any defect in material and workman

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Rev. 1.43 User's Guide 13115 Appendix 15.1. Application examples with the VSBC-6862 15.1.1. Example A: Application with VME boards

VSBC-6862 Rev 1.43 132 15.1.2. Example B: Application with non-VME boards The SBC-6860 is a single board computer, VME bus tolerant from ACT

Rev. 1.43 User's Guide 13315.1.3. Example C: Application in stand-alone The VSBC-6862 can be used in stand-alone mode. The followin

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Rev. 1.43 User's Guide 13516 Index Board configuration jumpers ...

VSBC-6862 Rev 1.43 136 jumpers ...

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Rev. 1.43 User's Guide 132 Peripherals description The VSBC-6862 offers a wide choice of on-board peripheral or bus interface, whic

VSBC-6862 Rev 1.43 14 2.3. SRAM memory 1 MBytes of SRAM memory are provided on-board, this memory is controlled with the Chip Select 9. This m

Rev. 1.43 User's Guide 15 The IP interface uses two processor chip selects to address all IP module spaces. The Chip Select 4 is used

VSBC-6862 Rev 1.43 16 The VME interrupter I(1-7) The interrupter is able to generate any VME IRQ level and send a user-defined vector. The V

Rev. 1.43 User's Guide 172.8. I2C EEPROM 8 kbits of non-volatile memory is provided on the I2C bus. This memory is used for board

VSBC-6862 Rev 1.43 18 2.11. SCC multi-protocols serial ports The VSBC-6862 offers four independent serial ports. In synchronous mode, all fou

USER'S GUIDE VSBC-6862 VME Single Board Computer with PowerQUICC II processor Revision 1.43 3105 ACTIS Computer www.actis-computer

Rev. 1.43 User's Guide 192.12. I2C interface The VSBC-6862 provides an I2C interface bus for on-board serial EEPROM accesses and use

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Rev. 1.43 User's Guide 213 Connectors & jumpers This chapter will describe all connectors and jumpers on the VSBC-6862. One of

VSBC-6862 Rev 1.43 22 Locations Figure 4: Connectors and jumpers location Artisan Technology Group - Quality Instrumentation ... Guaranteed |

Rev. 1.43 User's Guide 233.1. Push Button: BP1 In the front panel, the push button generates a Power-On Reset to the board. This bu

VSBC-6862 Rev 1.43 24 3.3. IP module strobes, header J1 For IP module operations, an optional "STROBE" signal is provided for each

Rev. 1.43 User's Guide 253.4. Jumper: J2 A jumper with six positions provides some basic functions. Figure 8: Jumper J2 location P

VSBC-6862 Rev 1.43 26 Position 4 VME Reset Out Factory seting Description Unplugged X Board is not authorized to generate a VME Reset Plugg

Rev. 1.43 User's Guide 273.6. Jumpers: J4, J5, J6, J7 This are the 'serial mode' jumpers, they have six position. They pe

VSBC-6862 Rev 1.43 28 3.7. Jumper: J8 This jumper sets the base address for the A16 slave window. This window contains all registers accessibl

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Rev. 1.43 User's Guide 293.8. Two RS-232 terminal ports, and I2C bus: P13, P4 These serial ports are provided for general purpose

VSBC-6862 Rev 1.43 30 The second serial port is available in an internal connector shared with the I2C bus. P4 contains the signals for the SM

Rev. 1.43 User's Guide 313.9. Four multi-protocols serial ports P7,P8,P9, P10 These four serial ports are provided for user applica

VSBC-6862 Rev 1.43 32 Termination network resistors When the RS-422/RS-485/V.35 is chosen, the VSBC-6862 is provided with removable network re

Rev. 1.43 User's Guide 333.10. Two Fast Ethernet ports, connectors P11, P12 For LAN based applications, two fast Ethernet connection

VSBC-6862 Rev 1.43 34 3.11. IEEE-1149.1 interface, connector P3 The MPC-8260 provides a dedicated user-accessible test access port (TAP) that

Rev. 1.43 User's Guide 353.12. VME bus, P1 connector Row A Row B Row C Pin Signal Pin Signal Pin Signal A1 D0 B1 /BBSY

VSBC-6862 Rev 1.43 36 3.13. VME bus, P2 connector This connector has its VME user's pins attributed to the IP I/O slot D Row A Row B

Rev. 1.43 User's Guide 37 Signal Description +5 V Main power supply +12 V Power used for IP module slots and Flash protection feat

VSBC-6862 Rev 1.43 38 3.14. Four IP module logic interface, connectors P3A, P4A, P5A, P6A For input/output extensions, the VSBC-6862 board pr

Rev. 1.43 User's Guide 3Table of contents 1 Product description _________________________________________________________ 7 1.1. In

Rev. 1.43 User's Guide 393.15. Four IP module I/O signals, connectors P3C, P4C, P5C, P6C The four IP modules slots present on the VS

VSBC-6862 Rev 1.43 40 3.16. Real time clock battery, circuit U5 The VSBC-6862 provides a real time clock for calendar function. This device

Rev. 1.43 User's Guide 413.17. Fuses protection The VSBC-6862 offers a flexible I/O extension facility through its quad IP module i

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Rev. 1.43 User's Guide 434 Software description 4.1. Introduction The PowerQUICC II includes a very versatile and powerful memory

VSBC-6862 Rev 1.43 44 4.2. FLASH memory Two banks of Flash devices are available. Each bank is 4 or 8 MBytes wide for a total of 8 or 16 MByte

Rev. 1.43 User's Guide 45Typical Option Register: Bit Field Value Function 0-16 AM $FFC0 0 Address mask: for 4 MBytes 1

VSBC-6862 Rev 1.43 46 4.2.3. FLASH chip erase Chip erase operation is accomplished by executing the erase command sequence. This will invoke th

Rev. 1.43 User's Guide 47With Flash type organization as: Sector Size for type 1 Size for type 2 Size for type 3 Size for type

VSBC-6862 Rev 1.43 48 4.3. SDRAM memory This memory is handled by the powerful SDRAM timing machine contained in the MPC-8260. The SDRAM mach

VSBC-6862 Rev 1.43 44.2.5. FLASH sector protection: option on request_________________________________ 47 4.3. SDRAM memory____________________

Rev. 1.43 User's Guide 49Typical Option Register: Bit Field Value Function 0-16 AM $FE00 0 Address mask: for 32 MBytes

VSBC-6862 Rev 1.43 50 4.4. SRAM memory The VSBC-6862 includes 1 MByte SRAM for fast exchanges with external VME masters. With its backup capa

Rev. 1.43 User's Guide 514.5. Real Time Clock with SRAM memory The VSBC-6862 includes a real time clock device, with as an addition

VSBC-6862 Rev 1.43 52 48T37V partial register map is: Base + D7 D6 D5 D4 D3 D2 D1 D0 Function (Range) BCD format $7FFF 10 Years Yea

Rev. 1.43 User's Guide 53The Watchdog can be activated by setting the RTC's Watchdog register (internal offset $7ff7) with the d

VSBC-6862 Rev 1.43 54 4.6. IP modules The VSBC-6862 board provides four IP module slots, which are compliant with the ANSI/VITA 4-1995, except

Rev. 1.43 User's Guide 55The IP interface uses two processor chip selects to cover all IP module spaces. The I/O, ID, and INT spaces

VSBC-6862 Rev 1.43 56 Typical Option Register: Bit Field Value Function 0-16 AM $FE00 0 Address mask: for 32 MBytes 17-18 Reserv

Rev. 1.43 User's Guide 574.6.1. Memory spaces Partial Chip Select 4 memory map: Offset Description $000 - $07e IP module A: IO zon

VSBC-6862 Rev 1.43 58 With: The GCRx registers allow configuration of the IP module main capabilities, as following: ENIRQ bit: When set,

Rev. 1.43 User's Guide 57 Registers definition ________________________________________________________ 99 8 Characteristics ________

Rev. 1.43 User's Guide 594.6.4. DMA functions The DMA is controlled by the IDMA channels of the MPC-8260. The DCR registers set-up

VSBC-6862 Rev 1.43 60 Board control registers The VSBC-6862 contains some registers for general board features. They are mapped in the Chip S

Rev. 1.43 User's Guide 614.7. VME operations The VSBC-6862 includes also modules to handle VME operations. There is VME master, slav

VSBC-6862 Rev 1.43 62 4.7.3. VME master The VSBC-6862 is VME master A32/A24/A16/D32/D16/D8 The VME master can use two windows to access the V

Rev. 1.43 User's Guide 63Typical Option Register: Bit Field Value Function 0-16 AM $FC00 0 Address mask: for 64 MBytes

VSBC-6862 Rev 1.43 64 4.7.4. VME slave The VSBC-6862 is slave A16/A24/D32/D16/D8. The board contains an independent slave module. This module

Rev. 1.43 User's Guide 65The A24 window This window contains Flash, SRAM, and RTC zones. This window occupies 1 MBytes and must

VSBC-6862 Rev 1.43 66 The VMEA24 Slave window accepts the 'pseudo-RMW' cycles as described on the VME master chapter. We also implem

Rev. 1.43 User's Guide 674.7.8. VME system controller The VSBC-6862 can work as a system controller. This function can be enabled or

VSBC-6862 Rev 1.43 68 4.8. Serial I2C EEPROM 8 kbits of non-volatile memory is provided on the I2C bus. This memory can be used for board init

VSBC-6862 Rev 1.43 6List of figures Figure 1: Photograph...

Rev. 1.43 User's Guide 694.9. Fast Ethernet ports 4.9.1. Transceivers description The two fast Ethernet interfaces come directly f

VSBC-6862 Rev 1.43 70 4.9.2. MPC-8260 I/O ports The following table gives the connection to MPC-8260 I/O ports. MPC-8260 Peripheral functi

Rev. 1.43 User's Guide 714.9.3. Transceivers operations Each transceiver has many registers to handle Fast Ethernet operation. Thes

VSBC-6862 Rev 1.43 72 PHY register address 1: Status Register Bit NAME DESCRIPTION R/W DEFAULT 15 100BASE-T4 1 = 100BASE-T4 capabilit

Rev. 1.43 User's Guide 73PHY register address 4: Auto-Negotiation Advertisement Register Bit NAME DESCRIPTION R/W DEFAULT 15

VSBC-6862 Rev 1.43 74 LED Function: Description for PHY register 17, bits 7 and 6 Bits 7, 6 LED_5 LED_4 LED_3 LED_2 LED_1 LED_0 11 Rec

Rev. 1.43 User's Guide 754.10. SMC1 and SMC2 serial ports One of these general-purpose serial ports is available on the front panel

VSBC-6862 Rev 1.43 76 4.11. SCC serial ports The VSBC-6862 offers four independent serial ports. In synchronous mode, all four ports have ind

Rev. 1.43 User's Guide 774.11.2. RS-422/RS-485/V.35 option These VSBC-6862 ports are compatible with these three modes. The followin

VSBC-6862 Rev 1.43 78 4.11.3. ACTIS Serial Cable ACTIS can provide a serial cable for these multi-protocol serial ports. Its reference is CAB

Rev. 1.43 User's Guide 71 Product description 1.1. Introduction Today industrial applications are growing in telecom market due to

Rev. 1.43 User's Guide 794.11.4. MPC-8260 I/O ports The following table gives the connection to MPC-8260 I/O ports. MPC-8260 Pe

VSBC-6862 Rev 1.43 80 4.12. I2C interface The VSBC-6862 provides an I2C interface bus for on-board serial EEPROM accesses and user purposes. F

Rev. 1.43 User's Guide 815 Summary of board resources 5.1. Chip Select Chip Select Port size (bits) Device Size CS0 32 Flash b

VSBC-6862 Rev 1.43 82 With: Local offset: offset from local CS4 VME offset: offset from VME A16 slave window, defined with J8 Mode: R

Rev. 1.43 User's Guide 83The VSBC-6862 uses these reset signals with an equivalent circuitry than following: Figure 21: Reset schem

VSBC-6862 Rev 1.43 84 5.5. Power description For the majority of the applications, the VSBC-6862 uses only the +5V power supply. Internally, m

Rev. 1.43 User's Guide 855.7. MPC-8260 I/O ports assignment The MPC-8260 processor provides four I/O ports (A, B, C and D) which h

VSBC-6862 Rev 1.43 86 PD10 BRG4 O TxC Transmit clock PC26 CLK6 I RxC Receive clock Fast Ethernet port 1 PB6 MII_MDC O ECMDC data clock PB7 M

Rev. 1.43 User's Guide 87PA5 IDMA4: DREQ I DMARQ4 IDMA request PD6 IDMA1: DACK I DMACK1 IDMA acknowledge PC3 IDMA2: DACK I DMAC

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VSBC-6862 Rev 1.43 81.2. Features This board has been designed to integrate the most required functions, including several Fast Ethernet port

Rev. 1.43 User's Guide 896 Board initialization The VSBC-6862 must set up the specific hardware organization for the PowerQUICC II p

VSBC-6862 Rev 1.43 90 6.2. Reset Word The ResetWord is a 32 bits field read by the PowerQUICC II during Power-On sequence. This word set sever

Rev. 1.43 User's Guide 916.3. MPC-8260 internal registers The MPC-8260 contains some registers to configure for correct operations.

VSBC-6862 Rev 1.43 92 SIU Module Configuration Register: SIUMCR This register contains bits that configure various features in the SIU modu

Rev. 1.43 User's Guide 936.4. MPC-8260 I/O ports The PowerQUICC II contains 120 I/O pins that are used for communication ports and

VSBC-6862 Rev 1.43 94 PB12 SCC2_TXD 1 1 0 1 PB13 not used 0 1 0 0 PB14 SCC3_RXD 1 0 0 0 PB15 SCC2_RXD 1 0 0 0 PB16 not used 0 1 0 0 PB1

Rev. 1.43 User's Guide 95PC30 LED_AUX1 0 1 0 0 PC31 SCC1_TXCLK 1 1 0 0 I/O Function PPARD PDIRD PODRD PSORD PD4 not used 0 1

VSBC-6862 Rev 1.43 96 6.5. Chip select Before accessing a internal peripheral, the corresponding chip select must be initialized. The descrip

Rev. 1.43 User's Guide 97Serial Number Option (optional) This option specifies the serial number of the product (ASCII terminated b

VSBC-6862 Rev 1.43 98 6.7. Boot code The boot code is mapped as standard PowerPC map. The exception table is located from offset $0100 to $2F